The invention generally relates to integrated circuit chips and media for interconnecting same. More particularly, the invention relates to assemblies known as multichip modules (MCM) wherein unpackaged integrated circuit chips can be mounted on and wired to a substrate containing multiple patterned metal levels for power distribution and signal interconnection.
An MCM generally comprises a substrate on which are formed patterned conductive regions for the interconnection of circuit components, usually integrated circuit chips. The conductive regions are usually made of metal and formed in multiple levels, referred to herein as metal or interconnection levels or layers.
It is known that a substrate of an MCM can be fabricated of a variety of materials such as silicon, ceramic (for example, alumina), glass, or metal (for example, aluminum). It is also known that an interconnection level or layer can be formed on the substrate by depositing a conductive region on a given layer using techniques such as sputtering, evaporating, and in combination sputtering and plating. The conductive region then can be patterned into signal and power distribution conductors by photolithographic techniques combined with etching or selective plating. Multiple interconnection levels or layers can be formed so long as suitable interposing insulating layers are provided.
Interposing levels of insulating dielectric, i.e., insulating layers disposed between interconnection layers, can be applied by spinning, in the case of polymers, or chemical or physical vapor deposition, in the case of inorganics such as silicon dioxide. Holes (vias) patterned in these insulating layers by photolithography and wet or dry etching techniques allow interconnection from one level of metal to another.
An MCM substrate assembly as described above provides an interconnection medium for a plurality of chips that is more advantageous than, for example, printed circuit boards to which are mounted individually packaged chips, because it dramatically reduces the distance required for signals to travel between chips, and thus the time delay for inter-chip signal propagation. As integrated circuit technology has continued to advance to higher circuit speeds, this interconnection delay has become a major limitation on system performance, and thus has increased the importance of MCMs as interconnection media.
Also, for electronic systems, the use of an MCM and unpackaged chips advantageously results in far greater packing density of chips, and thus reduced system size.
A disadvantage of present MCM packaging and interconnection systems has been the high cost of MCM fabrication. The fabrication process is similar to that for integrated circuits (IC), and manufacturing equipment designed for integrated circuits generally has been used to fabricate MCMs, although an older generation of equipment generally can be used since MCM feature sizes are considerably larger than IC feature sizes. The manufacturing process of MCMs is essentially sequential, and the cost is roughly proportional to the number of photolithographic masks used in fabrication.
In this regard, it is common practice for MCM manufacturers to use at least four metal or interconnection levels, and thus eight or more masks, to provide for both power distribution and signal interconnections. Typically, there is one level each for a power plane, a ground plane, signals in the X direction, and signals in the Y direction. A mask is used for each level to pattern the conductive regions or conductors, and then another mask is used at each level to pattern the holes (vias) in the intervening dielectric to the next interconnection level.
The uppermost layer of an MCM usually is a dielectric which protects the entire structure, and whose pattern of openings to underlying conductive regions allows connections to be made between chips or the MCM package and the substrate itself by means of wire bonds, solder bumps, or other interconnection means.
In some MCM manufacturing technologies, additional masks are required for top level metallization compatible with wire bond or solder interconnect processes. It is also common to include some form of capacitor dielectric for decoupling purposes between the large area power and ground planes, and this dielectric must be patterned with yet another mask. All of these mask levels contribute to fabrication complexity and cost, and each manufacturing step in some incremental manner contributes to the inevitable yield loss due to manufacturing defects.
The combined maximum wiring density in a set of MCM signal planes generally can exceed 2,000 inches of wire per square inch of substrate. Yet, except in areas of the highest wiring congestion, most MCM designs use only a fraction of the available wiring capacity on the signal planes.
It is known that a pair of solid power distribution planes, one plane for power and one plane for ground, form an extremely low inductance power distribution system for relatively noise-free power delivery to semiconductor chips. It is also known that sandwiching a thin layer of dielectric material between these planes creates a distributed decoupling capacitor with very good high frequency characteristics. For example, see U.S. Pat. No. 4,675,717, the disclosure of which is incorporated herein by reference. Further, advances in discrete capacitor technology have resulted in decoupling capacitors with extremely low internal inductance. The use of these capacitors with a pair of power distribution planes also can result in a relatively noise-free power distribution environment. For example, see Tummala, et al. xe2x80x9cCeramics Packaging with Ferroelectric Decoupling Capacitorxe2x80x9d, IEEE International Symposium on Applications of Ferroelectrics, 1990, pp. 28-30, the disclosure of which is fully incorporated herein by reference.
It is also known that a solid power distribution plane can be perforated with an array of holes with little change in the electrical characteristics thereof. Such planes are commonly used in MCMs on layers which overlay polymer dielectrics, to allow outgassing of the polymer during curing. The resulting structure is known as a mesh plane.
Further, both power and ground potentials can be distributed on one physical layer by means of a technique referred to as interdigitation. In interdigitation, long, thin conductive regions are provided on one layer for carrying power and ground potentials or signals. The power and ground regions are, for example, alternately arranged so that every other region carries power potentials or signals while the interposing regions carry a ground potential. In this technique, however, if the conductors are long and thin, parasitic inductance and resistance detrimental to noise-power-free distribution are introduced. See H. Schettler, xe2x80x9cPassive-Silicon-Carrier Design and Characteristicsxe2x80x9d, 40th Electronic Components and Technology Conference, Las Vegas, May 20-23, 1990, pp. 559-561.
The present invention provides an interconnection medium wherein the number of interconnect layers is reduced while the low inductance power distribution characteristics of parallel power and ground planes, as well as the high wiring density for signal interconnect wires characteristic of photolithographic fabrication techniques are retained.
To that end, the present invention inventively combines aspects of mesh planes and interdigitation to create what is referred to herein as dual offset mesh planes or an interconnected mesh power system. The word xe2x80x9cdualxe2x80x9d denotes the provision of both power and ground planes. The word xe2x80x9coffsetxe2x80x9d denotes the appearance of conductive regions of one electrical plane on two different interconnect layers.
As explained below, in a single offset mesh plane, all X direction conductors are carried on a first metal layer, and all Y direction conductors are carried on a second metal layer. At each point where these conductive regions overlie one another, they can be interconnected by means of a conducting hole or via through the dielectric separating the two metal layers. These conductive regions thus can define one electrical plane. Another plane can be incorporated into the structure by interdigitating in both metal levels a conductive region of opposite polarity between every conductor region of the first plane, and similarly connecting the overlying regions with vias to provide two offset mesh planes. Thus, the two metal levels can contain the electrical equivalent of two mesh planes, with the critically important topological feature that all conductive regions (i.e., conductors) lying in a given metal layer run in the same direction.
These features allow signal conductors to be effectively woven into a fabric of power and ground conductors. During the design process, when a signal path must be included between two points, the designer can determine the necessary X and Y conductors which must be included in the signal path and then isolate portions of the power and/or ground conductors on the metal layers necessary to provide a signal path. Of course, this process can be automated-specifically, computer-implemented-with the use of a computer aided design (CAD) system.
To this end, the present invention provides a method of forming a multichip module by computer-implemented design, which includes providing a first planar layer having a plurality of first groups of conductive regions arranged in a parallel, interdigitated manner with a plurality of second groups of conductive regions. A second planar layer is provided having a plurality of third groups of conductive regions arranged in a parallel, interdigitated manner with a plurality of fourth groups of conductive regions. The conductive regions in the second layer run generally perpendicularly to the conductive regions of the first layer. A section of at least one selected conductive region is removed to form at least one signal conductor.
In an embodiment, the conductive regions are initially spaced from one another.
In an embodiment, respective spaces between like conductive regions of the first and third groups are filled with conductive material after the removing step. This forms a single contiguous ground conductor from each first and third group. Also, spaces between conductive regions of the second and fourth groups are filled with conductive material after the removing step, forming a single contiguous power conductor from each second and fourth group. These spaces are not filled adjacent to each signal conductor, such that each signal conductor is spaced from adjacent power and ground conductors.
In an embodiment, each group is a pair.
In an embodiment, a plurality of vias is provided to connect overlapping junctions of conductive regions of the first groups and conductive regions of the third groups. Also, a plurality of vias is provided to connect overlapping junctions of conductive regions of the second groups and conductive regions of the fourth groups.
In an embodiment, at least one of the signal conductors is in the first layer and at least one of the signal conductors is in the second layer. At least one via is provided to join (connect) an overlapping junction of the signal conductor in the first layer and the signal conductor in the second layer. It should be understood that those steps of xe2x80x9cremovingxe2x80x9d and xe2x80x9cfillingxe2x80x9d are performed in the computer aided design (CAD) system, not on a physical device.
In another embodiment, a method of forming a multichip module by computer-implemented design is provided, including providing a first planar layer having a plurality of first conductive regions arranged in a parallel, interdigitated manner with a plurality of second conductive regions such that edges of adjacent first and second conductive regions touch each other. A second planar layer includes a plurality of third conductive regions arranged in a parallel, interdigitated manner with a plurality of fourth conductive regions such that edges of adjacent third and fourth conductive regions touch each other. The conductive regions in the second layer run generally perpendicularly to the conductive regions in the first layers. Areas are then defined along selected borders of the touching edges, representing desired signal conductor paths. Conductive material is then removed from the conductive regions to form a space between adjacent conductive regions and a space between each area and adjacent conductive region.
The present invention also provides an improved MCM which can be constructed according to the preceding method. To this end, an electrical interconnection medium is provided including first and second interconnecting layers. Each layer has a plurality of parallel isolated signal conductive regions and interdigitated first and second conductive regions. At least one of the layers has a plurality of uniformly spaced parallel longitudinal axes throughout the layer. Each axis is located centrally between adjacent first and second conductors. Each of the isolated signal conductors is aligned on one of the axes.
In an embodiment, the conductive regions of the second layer are oriented orthogonally to the conductive regions of the first layer.
In an embodiment, the first conductive regions of the first and second layers are electrically interconnected at overlapping junctions by vias to form a power plane. Also, the second conductive regions of the first and second layers are electrically interconnected at overlapping junctions by vias to form a ground plane.
In an embodiment, the isolated signal conductive regions of the first and second layers are electrically connected at selected overlapping junctions.
The present invention also provides a computer-implemented design method for forming a multichip module which has two distinct power grids as well as a ground mesh and signal conductors. For example, one of the power grids could deliver 5V and the other could deliver 3.3V. To this end, in an embodiment, a method of forming a dual power grid multichip module includes providing a first planar layer having a plurality of first groups of conductive regions arranged in a parallel, interdigitated, sequential manner with a plurality of second groups and third groups of conductive regions. A second planar layer is provided having a plurality of fourth groups of conductive regions arranged in a parallel interdigitated, sequential manner with a plurality of fifth groups and sixth groups of conductive regions. The conductive regions in the second layer run generally perpendicularly to the conductive regions in the first layer. A section of at least one selected conductive region is removed to form at least one signal conductor.
In an embodiment, the conductive regions are initially spaced from one another. In a related embodiment, respective spaces between like conductive regions of the first and fourth groups are xe2x80x9cfilledxe2x80x9d after the removing step with conductive material, forming a single contiguous ground conductor from each first and fourth group. Respective spaces between like conductive regions of the second and fifth groups are xe2x80x9cfilledxe2x80x9d after the removing step with conductive material, forming a single contiguous first power conductor from each second and fifth group. Respective spaces between like conductive regions of the third and sixth groups are xe2x80x9cfilledxe2x80x9d after the removing step with conductive material, forming a single contiguous second power conductor from each third and sixth group. Each signal conductor is spaced from adjacent ground conductors and first and second power conductors. A plurality of vias are provided to connect overlapping junctions of conductive regions of the first and fourth groups. A plurality of vias are provided to connect overlapping junctions of conductive regions of the second and fifth groups. A plurality of vias are provided to connect overlapping junctions of conductive regions of the third and sixth groups.
In an embodiment, at least one signal conductor is formed in the first layer and at least one signal conductor is formed in the second layer. The method further includes providing at least one via to join an overlapping junction of the signal conductor in the first layer and the signal conductor in the second layer.
In an embodiment, a method of forming a dual power grid multichip by computer-implemented design includes providing a first planar layer including a plurality of first conductive regions arranged in a parallel, interdigitated, sequential manner with a plurality of second conductive regions and third conductive regions such that borders of adjacent first, second and third conductive regions touch each other. A second planar layer is provided including a plurality of fourth conductive regions arranged in a parallel, interdigitated, sequential manner with a plurality of fifth conductive regions and sixth conductive regions such that borders of adjacent fourth, fifth and sixth conductive regions touch each other. The conductive regions in the second layer run generally perpendicularly to the conductive regions in the first layer. Signal path areas are defined along selected borders. Conductive material is removed from the conductive regions to form a space between adjacent conductive regions and a space between each signal path area and adjacent conductive regions. A plurality of vias are provided to connect overlapping first and fourth conductive regions. A plurality of vias are provided to connect overlapping second and fifth conductive regions. A plurality of vias are provided to connect overlapping third and sixth conductive regions. Also, at least one via is provided at a selected junction of the signal path areas.
These and other features of the present invention are set forth in greater detail in the following detailed description of the presently preferred embodiments and accompanying drawings.